The present invention relates generally to a computer processing system, and more specifically to a multi-use physical (PHY) architecture in a computer processing system.
Computer and communication systems often have components that are “input/output (I/O) bound” or “pin limited.” This means that, for example, a microprocessor may be unable to implement all of the functions that are desired due to limitations in the physical size of the silicon, or that the packaging of the chip prevents implementation of the needed number of I/O's. In contemporary system architectures interface buses are generally designed for a specific purpose. For instance, systems often contain dedicated processor interconnect buses, and separate memory buses. In many cases multiple architectures must be implemented to support varied functionality. For example, a lower end system may require fewer processor interconnects, while higher end systems may require more processor interconnects and a large amount of memory. These requirements are often determined by the system configuration and/or by the customer price/performance point that is desired. In these cases, despite implementing similar processor and memory systems for both high-end and lower end systems, the bus systems must be designed differently in order to support each of the customer requirements.
In contemporary memory systems, differing memory devices can be used on a single bus when that bus supports such capabilities. For example, an un-buffered memory dual in-line memory module (DIMM) can be attached to the same bus that a buffered memory DIMM can be attached to, as long as industry standard timing parameters are adhered to for each of the different memory modules. This flexible configuration capability, however, it is not possible between memory modules and computer processors due to incompatible voltage levels and bus design (e.g., single-ended buses vs. differential buses).